1. Field of the Invention
This invention relates generally to a power converter and more particularly to a phase control device for a power converter.
2. Description of the Prior Art
A power converter including controlled rectifier elements may be operated either as a rectifier or as an inverter by the individual control of firing phases of the respective controlled rectifier elements. FIG. 1 shows a power converter 1 which includes controlled rectifier elements connected in three-phase bridge connection, such as thyristors U, V, W, X, Y and Z. In FIG. 1, when the power converter 1 is operated as a rectifier, an AC power received from AC terminals R, S and T is converted into a DC power which is outputted to DC terminals N and P. On the contrary, when operating as an inverter, a DC power received from the DC terminals N and P is converted into an AC power, which is outputted to the AC terminals R, S and T.
A phase control device for controlling firing phases of the respective controlled rectifier elements in a power converter has conventionally employed an AC-DC superimposed method in analog fashion. Recently, however, significant developments in digital technology, particularly in microcomputers and memory elements, cause such a phase control device to be digitized.
FIG. 1 also shows a digital-type phase control device 2 type for controlling the firing phases of the thyristors U, V, W, X, Y and Z. The phase control device 2 receives, through potential transformers 5R, 5S and 5T, AC voltage signals e.sub.R, e.sub.S and e.sub.T which are in-phase with respect to voltages across the AC terminals R, S and T, respectively. The phase control device 2 also receives a DC current of the power converter 1 through a current transformer 6 as a feedback signal FED. Instead of the DC current of the power converter 1, an AC voltage, an AC current or a DC voltage of the power converter 1 may be used as the feedback signal FED. The phase control device 2 further receives a reference signal REF and produces a firing pulse TP to control the firing phases of the thyristors U, V, W, X, Y and Z of the power converter 1 based on the AC voltage signals e.sub.R, e.sub.S and e.sub.T, the feedback signal FED and the reference signal REF. The firing pulse TP includes firing pulses TPU, TPV, TPW, TPX, TPY and TPZ, which are applied to gates of the thyristors U, V, W, X, Y and Z, respectively.
FIG. 2 shows a digitized construction of the phase control device 2 in detail. In FIG. 2, the phase control device 2 includes a digital phase detector 10, a digital processing circuit 11 and a firing pulse determination circuit 12. The firing pulse determination circuit 12 includes a digital comparator 13 and a gate logic circuit 14. The phase detector 10 receives the AC voltage signals e.sub.R, e.sub.S and e.sub.T from the power converter 1 through the potential transformers 5R, 5S and 5T, respectively, and produces a digital phase signal .theta. in synchronism with the received AC voltage signals e.sub.R, e.sub.S and e.sub.T. The digital phase signal .theta. includes a phase synchronizing signal .theta.1 and a phase judging signal .theta.2. The digital processing circuit 11 receives the feedback signal FED through the current transformer 6 from the power converter 1 and the reference signal REF, and produces a digital phase control signal Ec so that the feedback signal FED becomes equal to the reference signal REF. The digital processing circuit 11 is usually constructed with a microcomputer, as will be described later in detail. The digital phase control signal Ec includes a control signal .delta.1 and an angle signal .delta.2. The digital comparator 13 in the firing pulse determination circuit 12 compares the phase synchronizing signal .theta.1 from the digital phase detector 10 with the control signal .delta.1 from the digital processing circuit 11, and outputs a pulse COM when the value of the phase synchronizing signal .theta.1 is larger than or equal to the value of the control signal .delta.1 (.theta.1.gtoreq..delta.1). The gate logic circuit 14 receives the phase judging signal .theta.2 from the digital phase detector 10, the pulse COM from the digital comparator 13 and the angle signal .delta.2 from the digital processing circuit 11 and produces the firing pulse TP so as to control the firing phases of the thyristors U, V, W, X, Y and Z in the power converter 1.
FIG. 3 shows an example of a detailed configuration of the digital phase detector 10 shown in FIG. 2. In FIG. 3, the digital phase detector 10 has a conventional so-called phased locked loop circuit, in which the frequency of an output pulse of a voltage control oscillator 22 is devided by 2.sup.8 (=256) by a counter 33. The frequency of an output pulse of the counter 23 is further divided by six by a counter 24. The count of the counter 24 is applied to a decoder 25 which produces three-phase output signals e.sub.1R, e.sub.1S and e.sub.1T. These three-phase output signals e.sub.1R, e.sub.1S and e.sub.1T are compared in terms of the respective phases, with the AC voltage signals e.sub.R, e.sub.S and e.sub.T in phase comparators 17, 18 and 19, respectively. The phase differences thus obtained in the phase comparators 17, 18 and 19 are added up in an adder 20 to produce an added signal. The added signal is applied to a loop filter 21, which derives a DC component from the added signal. The derived DC component is applied to the voltage control oscillator 22 to control the frequency of the output pulse thereof.
The above-described configuration allows that the outputs of the counters 23 and 24 and the output of the decoder 25 become synchronous with the three-phase AC voltage signals e.sub.R, e.sub.S and e.sub.T. The counter 23 repeats counting from 0 to 255 in synchronism with an electrical angle of 60.degree. of the AC power source voltage, and the output signal of the counter 23 is the phase synchronizing signal .theta.1 of 8-bit binary. The counter 24 receives a carry signal SYNC from the counter 23 and the output signal of the counter 24 is the phase judging signal .theta.2.
FIG. 4 shows a detailed configuration of the digital processing circuit 11 shown in FIG. 2. The digital processing circuit 11 includes a computer 30 and a sampling pulse generator 35. The computer 30 includes a central processing unit 31, a memory unit 32, an input port 33 and an output port 34. The central processing unit 31 receives the reference signal REF and the feedback signal FED through the input port 33 at every reception of a sampling pulse SMP from the sampling pulse generator 35, and performs a specified calculation based on the programs and the data stored in the memory unit 32, then it outputs the calculated result as the digital phase control signal Ec through the output port 34. The digital phase control signal Ec is a 10-bit binary signal. The upper two bits thereof are utilized as the angle signal .delta.2 and the lower eight bits thereof are utilized as the control signal .delta.1.
The control signal .delta.1 thus obtained is compared with the phase synchronizing signal .theta.1 from the counter 23 of the digital phase detector 10 in the digital comparator 13, which produces the pulse COM when .theta.1.gtoreq..delta.1.
The phase judging signal .theta.2 from the counter 24 is of a hexary code, and the angle signal .delta.2 which is the upper two bits of the digital phase control signal Ec is of a ternary code, as shown in Table 1.
TABLE 1 ______________________________________ .theta.2 0 1 2 3 4 5 .delta.2 0 1 2 ______________________________________
One count of the phase judging signal .theta.2 corresponds to an electrical angle of 60.degree. of the line voltage, such as the line voltage e.sub.RS, of the AC power source provided with the AC voltage e.sub.R, e.sub.S and e.sub.T, respectively. Here, each of the thyristors U, V, W, X, Y and Z is controllable during the period of an electrical angle of 180.degree. of the AC power source voltage. When the period of 180.degree. is devided into three equal periods of 60.degree., the phase judging signal .theta.2 designates which period of the three the digital phase control signal Ec lies in.
On the basis of the value shown in Table 1, firing phases of the thyristors U, V, W, X, Y and Z in the power converter 1 are judged in the gate logic circuit 14 in such a manner as shown in Table 2.
TABLE 2 ______________________________________ .theta.2-.delta.2 0 1 2 3 4 5 -2 -1 firing U Z V X W Y phase ______________________________________
The gate logic circuit 14 judges a firing phase to be next fired based on the difference between the phase judging signal .theta.2 and the angle signal .delta.2 and feeds the firing pulses TPU, TPV, TPW, TPX, TPY and TPZ to the corresponding thyristors U, V, W, X, Y and Z, respectively.
FIG. 5 is a diagram to explain the process of firing phase determination in the firing pulse determination circuit 12. The phase synchronizing signal .theta.1 repeats counting from 0 to (2.sup.8 -1) at every one-sixth period of the AC power source, i.e., at every 60.degree. of an electrical angle, in synchronism with the AC power source line voltage e.sub.RS. On the other hand, since the phase judging signal .theta.2 counts the carry signals SYNC of the 8-bit binary counter 23, triangular waves shown in FIG. 5 may be considered as numerically designated. So the values of the phase judging signal .theta.2 are represented as the reference numerals of the triangular waves. In this connection, the digital phase signal .theta. is shown in a two-dot chain line. The digital phase control signal Ec may be considered to vary in such a manner as shown in a solid line Ec when the angle signal .delta.2 is represented as shown on the left side of FIG. 5.
Here, the firing pulses TPU, TPV, TPW, TPX, TPY and TPZ for the respective thyristors U, V, W, X, Y and Z of the power converter 1 in FIG. 1 may be obtained as follows. For example, the firing pulse TPU for the thyristor U should be outputted in accordance with the digital phase control signal Ec during the period of either triangular wave 0, 1 or 2, namely during the period of the electrical angle of 180.degree. of the AC power source voltage e.sub.RS. This means that the gate logic circuit 14 judges the firing phase based on the status of both the angle signal .delta.2 and the phase judging signal .theta.2 at the time when the pulse COM is outputted from the digital comparator 13. This is illustrated in FIG. 5 in such a manner that the control signal .delta.1 is shown as a dotted line.
The pulse COM is outputted at the time when the dotted line representing the control signal .delta.1 intersects the triangular wave representing the phase synchronizing signal .theta.1. The gate logic circuit 14 determines which of the thyristors U, V, W, X, Y and Z is to be fired and outputs the firing pulse TPU, TPV, TPW, TPX, TPY or TPZ to the determined thyristor U, V, W, X, Y or Z.
The power converter 1, the phase control device 2, the digital phase detector 10, digital processing circuit 11 and, the firing pulse determination circuit 14 shown in FIGS. 1-4 are all conventional and are will known to those skilled in the art. Thus the more detailed explanation thereof will be omitted.
Hereinafter we will describe the cases when failures occur in the conventional phase control device 2. Firstly, when the phase control signal Ec outputted from the digital processing circuit 11 becomes an erroneous signal before being applied to the firing pulse determination circuit 12 because of noise disturbances or the like, the firing pulses TP are outputted in a specified order to the respective thyristors U, V, W, X, Y and Z in the power converter 1. In this case, the firing pulses TP are outputted at the firing periods different from the firing periods at which the normal firing pulses TP are outputted based on the normal phase control signal Ec. The power converter 1 is operated based on the erroneous firing pulse TP, assuming that the firing pulse determination circuit 12 receives the phase control signal Ec normally, and produces the firing pulses TP normally. Therefore, the abnormalities in the phase control device 2 such as those in the digital phase control signal Ec can be detected only by the main circuit phenomena such as overvoltage or overcurrent caused by the power converter 1. Accordingly, there have been such disadvantages that the abnormalities of the phase control device 2 can be detected only after the occurrence in serious failures of the entire apparatus including the power converter 1, such as failures in frequency converters, electric motor systems or mechanical load apparatus driven by electric motors.
Secondly, even when the digital phase detector 10 has failed to cause the digital phase signal .theta. to be abnormal, or even when the firing pulse determination circuit 12 has failed so that it has produced no firing pulses TP or has produced the firing pulses TP neither in proper phase nor in proper order, such abnormalities of the phase control device 2 can be detected only by the main circuit phenomena caused by the erroneous operation of the power converter 1. Furthermore, in the conventional phase control device 2, it has been extremely difficult to detect specific failed portions within the phase control device 2 based on the main circuit phenomena because of the complicated circuit configuration of the phase control device 2.